SRAM cell design. EEPROM memory array design. Dram memory design.
Alopatek can design a custom cell and sense amp for your process. Our team can do full custom layout, test program generation and device / process consulting. We do SPICE simulation and examine how the design reacts to VDD noise, crosstalk, etc.

SRAM:
We also have high speed special circuits which can deliver very high performance to you SOC (system on a chip) using either static or dynamic circuit design. This is especially useful for high speed register files and high speed cache circuit design for microprocessor companies.
Other features:
Sense amps that go into a low power state when not being used.
Precharge and self timed logic.
All companies I know of have gone to six transistor cell rather than 4 transistor with resistive pullups.
Transistor sizing for high speed sense amps and reliable memory operation.
Mask effects on memory cell reliability.
We can provide small cell size with or without poly to N+ contact (buried contact).

EEPROM and EPROM:
Specializing in on chip charge pumps, redundancy, sense amps that work over a wide range of process, voltage and temperature. We can help you get either a single poly, double poly, or triple poly floating gate device memory designed and into production. We can also provide device engineering, run card, and full process engineering consultation.
If you have a fab and need a CMOS EEPROM process installed to run in your fab, email us.

DRAM:
Mask effects on memory cell reliability.
DRAM cells for ASIC stacked metal capacitors (as known as embedded memory) and standard trench CMOS memories.
DRAM sense amps (both clocked and self timed).

ROM:
Call Alopatek if you need to store boot code in a System on a chip (SOC) or other high density custom ROM.

Models for the above memorys can be supplied by us for usage in Verilog(TM of Cadence) or VHDL whole chip simulation.

Typical Design Contract:
-Schematics
-Layout database
-LVS/DRC run sets
-A design review
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