Julian Fields, Sunnyvale, CA 94087
julianfields at the domain yahoo is best for email.
PHONE: 1(408)773-8197, please use email rather than phone if you are a headhunter.
Verilog or SPICE chip design or verification
LOCATION: Silicon Valley (San Jose, Mountain View, Santa Clara,
Palo Alto, Cupertino, or Campbell) or anywhere via internet.
Might travel or relocate for exceptional contract or permanent
position.
I am mostly looking for contracts unless you have a management or super
senior position with income that can beat contracting.
SUMMARY: integrated circuit design / simulation work
experience and ASIC and memory design since 1980.
Over 14 first pass integrated circuit design successes.
Scored 790 out of 800 on math SAT.
Placed first in three state math tournament.
EDUCATION: Clemson Univ., BS Electrical and Computer Engineering,
Dec 1980.
Chip Design Consultant: (Jan 2003 - Present)
Consulting on various verilog logic design and digital
logic verification in verilog(tm)/PERL/vera(tm)/C.
Alopatek, Inc: (Jan 1997- Dec 2002) Asic and FPGA
verilog(tm)/Vera(tm)/Perl/Novas Debussy/Signalscan/C/
shell scripts design and verification, President
Contract for National Semiconductor (Fall of 2000
until July of 2002):
VERILOG (TM) design and VERA/Verilog/C PLI verification of a
Ultra Low Power Gigabit ethernet phy
(802.3 1000BASE-T) over
copper category 5 (physical layer) chip.
Responsible for MAC interface (SGMII, RGMII, GMII),
some fifos, various other design / simulation
tasks, regression farm management using PERL and
platform's LSF.
Simulation farm management using PERL and Platform LSF.
CVS source control. Vera(tm of Synopsys)
and verilog(tm of Cadence) system simulation
and verification. Formal verification equivalence
checking using Chrysalis(tm of Synopsys).
Also designed or verified 3 other chips which used
this as a core including a DP83864
Quad GigPHYTER 10/100/1000 Ethernet Physical Layer
http://www.national.com/pf/DP/DP83864.html
chip and the standard high volume production
product (DP83865 ULP GigPHYTER 10/100/1000 Ethernet
Physical Layer chip:
http://www.national.com/pf/DP/DP83865.html ) for sale
by National. SOC (System on chip) methodology.
For a Canadian Client: EEPROM and SRAM memory design
engineering. Lead engineer on the design of an EEPROM and
SRAM circuit design. Memory cell design. Sense amp design.
Charge pump design. Spice simulation, layout supervision.
On chip high voltage switching and voltage regulation.
Nonvolatile memory design and simulation.
CONTRACT: CISCO: (July 95 - July 96) ASIC engineer
Worked on 3 projects.
Simulate 7200 router motherboard and various boards
in Verilog.
Contained PCI bus, MIPs microprocessor, DRAM and SRAM cache
memory and ethernet chips, PCI bridge, Layer 3 switching, etc.
Verilog (TM), Viewlogic (TM), Atria, and Synopsys Logic Modeling
(TM) Models.
System simulation using real chips in a
hardware box (LM-1400 or Modelsource (TM)) that plays and
records vectors to an actual chip and feeds them to the simulator.
Simulation and verification of 2 other routers in MARS
Modular Access Router.
CONTRACT: 2nd time at APPLE: (March 95 - July 95), ASIC, Standard
cell Engr
Verification, synthesis and timing analysis of 2 ASICs for Pippin
Power Player.
Verilog interrupt logic design, memory controller testing
Regression setup, source control maintenance.
Synopsys (TM) script writing. Gate level debug. Rebuild Unix
kernel, etc.
Both chips worked first pass in our all new group of people and
new computers.
Worked on 400 Mbps IEEE 1394 Firewire (tm) chip for high speed
networking.
CONTRACT: 2nd time at QUANTUM (Jan. 94 - Feb. 95) ASIC design engineer
Synopsys (TM) and Verilog (TM) of 2 ASICs.
Added de- metastability logic.
Gate level sims, synthesis, conversion to TI and Chip Express
gate arrays.
Add timing checks to Verilog sims. Makefiles for synthesis.
PCMCIA block design. Regression testing. My block worked first
pass.
CONTRACT: 2nd time at LORAL ROLM MIL SPEC COMPUTER (Dec 92 - July 93)
Synthesis of large high speed gate array.
VHDL, Viewlogic (tm), Synopsys (tm) and LSI Logic CMDE (tm).
VHDL simulation of i860 interface and Crossbar gate arrays.
Multi-Chip Module selection. Spice of board level transmission
lines.
CONTRACT: ACUSON (Jan 92 - Dec 92) ASIC lead design engineer
Verilog (tm) and Synopsys (tm) of large standard cell from spec.
Sunrise Automatic Test Pattern Generation (ATPG) and boundary
scan design.
Wrote verification, regression scripts, makefiles, source control.
Wrote Synopsys batch queuing program.
C program to handle don't cares. Chip worked first pass.
Used Sun workstation, sole designer except for test vector help.
CONTRACT: SILICON GRAPHICS (Nov 91- Jan 92) CAD engineer
LCAP static timing verification, gate level simulation of 2 gate
arrays.
Floor planning in LSI Logic tools
Debug of Synopsys of Verilog (tm) link problems, etc. Chip worked
1st pass.
CONTRACT: LORAL ROLM MIL SPEC COMPUTER (Oct 90- June 91)
ASIC design engineer
Ikos board level simulation of 1.5 million gate pipelined (ten
gate arrays) computer
Clone of DG MV Eclipse32.
Used Sun workstation. 3 of 4 chips worked first pass.
Synopsys, Verilog(tm), IKOS system simulation of 600,000 gate
board
Design included 5 gate arrays (30K gates to 100K gates).
Teradyne Aida ATPG scan test pattern generation.
Fixed simulation model of RISC Mips R3000 (in house version).
Modeled misc board level components for simulation.
CONTRACT: ANDROS ANALYZERS: (Sept 90- Oct 90) FPGA Design Engineer
Actel field programmable gate arrays: Logic design, and simulated
2 FPGAs.
Orcad draft and VST simulate.
Contained UART, parallel ports, FIFOs, timers, maskable intr.,
for 68000.
Wrote C program to generate test vectors. Chips worked in time
for show.
CONTRACT: APPLE COMPUTER (Feb 89 - May 89) ASIC Design Engineer
Logic simulated 6 VLSI gate arrays. Taught new users of Mentor
Graphics.
CONTRACT: QUANTUM: (Jan 1988 - Feb 1989)
ASIC, Gate Array, Board debug, CAD Engineer
Design engineering on a chip and debug of one 1 board.
Helped logic design, test vectors of a disk controller 8,000 gate
array.
Test vectors for an IBM PC/AT interface gate array for high fault
coverage.
Debugged boards containing Intel 8096 microcontroller, SCSI, IBM-PC
bus, and ESDI
Used LSI Logic's LDS 6.2 software on Toshiba's IBM mainframe.
Put together CAE system of Mentor workstations, IKOS workstation,
and VGEN.
Used IKOS fault grading software.
CONTRACT: CAPSTONE TECHNOLOGY and MEMOREX: (Sept 87- Jan 88)
Logic designer / system engineer of an ASIC 5,400-gate gate array.
Wrote spec, did system partitioning and redesigned CRT / graphics
controller.
Logic design of video section of a color graphics 3270 terminal.
WAIT state logic, DMA logic for interfacing V40 to memories.
Made SRAMs dual-port by time slicing.
Included 6845 CRT controller
Had attribute logic for blinking, reverse video, cursor, print
box, and rule function.
Fastest chip (100 MHz) ever designed in National's 2 um CMOS.
Futurenet schematic capture, IBM mainframe (HI-LO simulator).
CONTRACT: VLSI TECHNOLOGY KLA INSTRUMENTS: (July 87) ASIC design
engr
Circuit designed precharged register file and high speed pad cells
of 32 MHz, 15K gate standard cell video processor.
Spice / layout supervision of integrated circuit.
CONTRACT: TRANSIMAGE INC: (a startup) (Jan 86 - Aug 86)
Optical character recognition firmware.
Part of computer architecture design team to define a custom VLSI
RISC processor
Implemented it in firmware and gate arrays for optical character
recognition
Cross assembled microcode on a DEC VAX using the Microtek Research
assembler.
Real time programming.
Used logic analyzers and Step Engineering emulator.
Debugged Pascal for 68000 using Tektronix 8540 in circuit emulator.
System level simulation for processor performance estimate.
Wrote VAX Pascal routines for TEK-HEX conversion.
Designed schematics for PC board with DRAMS, LED's, switches,
cabling, optics.
Checked plastic design for handheld optical scanner.
CONTRACT: Pistohl Electronic Tools:
Wrote assembly routines to interface IBM PC keyboard BIOS.
Helped setup an FIDO electronic bulletin board for customers.
CONTRACT: CALMA-GE: (June 85 - July 1985) CAD tools engineer
Fixed netlist problems between Calma's Tegastation and Cadence's
DRACULA by writing a set of shell programs.
ARRAY TECHNOLOGY (a small start-up), San Jose: Jan 84- Jan 85
Gate array design engr. (worked on 5 chips)
Part of 4 engineer team that did all engineering for a gate array
startup
Designed 2 chips for robotics, software protection, and bus arbitration.
Supported customers on 3 additional chips.
My chips worked on first pass.
Mentor workstation. Wrote test vectors. Estimated chip die sizes.
Cell library: Brought up new routers, new cells, and new simulation
models
Cadence's Dracula DRC and LVS: Responsible for getting LVS to
work
Wrote Unix-like shell programs to automate and to simplify place/route
(Cadiroute)
Pascal: Fixed Pascal netlister hashing program.
CONTRACT: INTERNATIONAL MICROCIRCUITS, Inc.: Aug 83- Dec 83
CMOS ASIC standard cell and gate array design engineer.
Logic/circuit design on a 16 by 16 parallel multiplier.
Designed a CMOS standard cell library using Applicon 860.
Redesigned a touch sensor with analog trip points and oscillators
for lamp dimmer.
NATIONAL SEMICONDUCTOR, Santa Clara: Feb 1982 - June 1983.
CMOS / NMOS Memory circuit design engineer. (involved with 4 chips)
Principal design engineer of 16K NMOS EEPROM (This was sold by
National as a 9817, a competitor to Intel's 2816).
Gained complete understanding of design rules and processing steps.
Designed 10 ms timer, 5V to 30V charge pumps, self test, state
machines
Designed redundancy circuits. All circuits fully on chip. Supervised
layout. The 9817 was a breakthrough chip which eliminated need for
external 22V programming supply, timers, and was much easier
to use.
Simulated the above on IBM mainframe. Did a design study
and simulation of nonvolatile static RAM (NOVRAM) which is a SRAM
with EEPROM inside to restore SRAM contents when power is lost.
HARRIS SEMICONDUCTOR, Melbourne, FL: 1980 - Feb 1982
CMOS IC design engineer (involved in 6 chips)
Standard cell library: Designed and laid out library for public
domain router MP2D
74HC00 Series: designed and laid out 4 chips using Calma GDS2.
Designed PLA of CPU Chip.
Spice: Used to design TTL buffers / standard cell library.
Programming: Wrote BASIC and FORTRAN statistics programs.
PROGRAMMING: Started in 1972 using BASIC and FORTRAN for four years.
Wrote the following programs:
FORTRAN to BASIC translator, Newton's
method to find x - intercept.
Microprogrammed an 8085 like instruction set on 2900 bit slice.
Microprogramming: 2900, optical char. recognition processor
Assembler: i8086, PDP-8
High level: BASIC, C, FORTRAN, PASCAL, Unix "C" shell
SIMULATORS: Verilog (tm), Futurenet, HILO, IKOS, LSI Logic, Mentor, Chronologic's VCS
Spice, VGEN, Compass
Verilog DUMP viewers: Novas Debussy, Undertow, SignalScan
FOUNDRIES: LSI Logic, National Semiconductor, Toshiba, VLSI Technology
PAPERS: IEEE JSSC, "A 16k EEPROM with redundancy", Oct 83
Thank you,
Julian Fields
julianfields at the domain yahoo is best for email.
VLSI Logic and Circuit Design Engineer
Verilog, VHDL, Synopsys, SPICE
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Memory design by Alopatek
Resume of our main UNIX development engineer.
Another version of the resume, but leaves this website.